In, for example, a device using Ultra Large Scale Integration (ULSI) technology and a Dynamic Random Access Memory (DRAM) using a short channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a leakage current may be increased when a transistor is turned-off due to a short channel effect. In addition, a contact resistance may increase due to a reduced active area, and process imbalance caused by a pattern density difference between regions in which different devices are formed may occur.
A semiconductor memory device can be divided into a cell region including memory cells and a peripheral circuit region including peripheral circuit devices. The peripheral circuit devices are configured for access operations of the memory cells in the cell region.
In a conventional semiconductor memory device, pattern density between the cell region and the peripheral circuit region is substantially different. Even when the pattern density within an area is the same, process imbalance may occur unless the pattern is uniformly distributed. A loading effect is generated through semiconductor device manufacturing processes such as, for example, a photolithography process, an etching process, a chemical mechanical polishing (CMP) process, a deposition process and a cleaning process, due to a pattern density difference between the cell region and the peripheral circuit region.
The loading effect causes etching rates changes due to pattern density difference. For example, in etching a gate line, a loading effect is generated in the peripheral circuit region due to a lower pattern density than in the cell region, thereby generating etching residues. A pattern density difference between the cell region and the peripheral circuit region may cause the occurrence of bridges in a bit line mask in the peripheral region.
A uniform critical dimension (CD) between devices is difficult to obtain due to the loading effect in processes such as photolithography and etching. In other words, a pattern formation deviation becomes large. For example, more than a targeted area can be etched in a peripheral circuit region.
In a conventional technology, a dummy pattern is formed within the peripheral circuit region to minimize the loading effect. A semiconductor memory device including a dummy pattern to minimize the loading effect will be described with reference to FIG. 1. FIG. 1 is a plan view of a conventional peripheral circuit region including devices for operating a memory cell.
Referring to FIG. 1, a peripheral circuit region 10 includes transistors 2 formed on an N-well, dummy patterns 4 to form a uniform pattern density, transistors 12 formed on a P-well and dummy patterns 14. The transistors 2 and 12 are configured to perform an access operation of memory cells in a semiconductor memory device.
The dummy patterns 4 and 14 are pseudo circuit patterns that are not used for an operation of a semiconductor memory device. The dummy patterns 4 and 14 are used to reduce a pattern formation deviation. Thus, the dummy patterns 4 and 14 are formed adjacent to the transistors 2 and 12. The dummy patterns 4 and 14 are provided for a uniform pattern density to reduce a loading effect in processes such as photolithography and etching so that a uniform CD between devices is ensured.
A pattern formation deviation is reduced by forming the dummy patterns 4 and 14. However, a region where transistors are not formed needs to be provided to obtain an efficient signal interface. A Metal Oxide Semiconductor (MOS) capacitor is formed on the region where transistors are not formed to provide a capacitance to prevent a noise signal.
FIG. 2 is a plan view schematically illustrating peripheral circuit regions including a peripheral circuit region 10 of FIG. 1.
With reference to FIG. 2, a region 30 not having transistors is provided to obtain an efficient signal interface between a peripheral circuit region 10 and another peripheral circuit region 20. In the region 30, a plurality of MOS capacitors 32 are formed. The MOS capacitors 32 stabilize a level of voltage in various direct current (DC) circuits to prevent a noise signal. Alternatively, a MOS capacitor is formed on an edge of a chip.
FIG. 3 is a block diagram including the MOS capacitor 32 shown in FIG. 2.
Referring to FIG. 3, a reference voltage generating circuit 51 includes a current mirror circuit unit 50, a reference voltage drive unit 60 connected between a power source voltage VDD and a first node N1, a reference voltage control unit 70 connected between the reference voltage drive unit 60 and a ground voltage VSS, and the MOS capacitor 32 connected between the first node N1 and the ground voltage VSS.
The MOS capacitor 32 of the reference voltage generating circuit 51 stabilizes a reference voltage VREF, i.e., a voltage between the reference voltage drive unit 60 and the reference voltage control unit 70. That is, the MOS capacitor 32 can maintain a desired reference voltage VREF when noise is applied to a power line and the power source voltage VDD becomes unstable.
The MOS capacitor 32 is applied to the reference voltage generating circuit 51 and to other DC circuits having an internal voltage converter (IVC) circuit. Since the MOS capacitor 32 stabilizes a voltage level, a semiconductor memory device can reliably operate.
However, due to high integration, space for a signal interface and the size of a dummy field to form a dummy pattern are reduced as a cell and a chip size become smaller. As a result, the size of the MOS capacitor is also reduced. Thus, a need exists for relocating the MOS capacitors in the semiconductor memory device.